The present invention relates to an internal supply voltage generating circuit and a method of generating an internal supply voltage. More particularly, it relates to an internal supply voltage generating circuit in a semiconductor memory device and an internal supply voltage generating method, which generate an internal supply voltage by dropping an external supply voltage and provide the individual circuits of the semiconductor memory device with the generated internal supply voltage.
Due to the micronization of the wiring pattern and the reduction in power consumption, a semiconductor memory device is provided with an internal supply voltage generating circuit which drops an external supply voltage to generate an internal supply voltage to be supplied to the individual internal circuits. The internal supply voltage generating circuit includes a reference voltage generating circuit and a voltage-drop regulator.
The reference voltage generating circuit generates a desired reference voltage from the external supply voltage and supplies the reference voltage to the voltage-drop regulator. The voltage-drop regulator receives the reference voltage and the external supply voltage and generates a stable internal supply voltage by dropping the external supply voltage in accordance with the reference voltage. The voltage-drop regulator supplies the internal supply voltage to various internal circuits via internal power lines.
It is desirable that a variation in the internal supply voltage be as small as possible. Therefore, the reference voltage, which is supplied to the voltage-drop regulator, should preferably have a high precision. However, there is a current of several micro amperes flowing in the reference voltage generating circuit and the threshold values of the individual transistors of the reference voltage generating circuit are not constant due to a productional variation. This results in a variation in reference voltage.
As a solution to reduce the variation in reference voltage, an internal supply voltage generating circuit having an internal reference generating circuit connected between a reference voltage generating circuit and a voltage-drop regulator has been proposed. The internal reference generating circuit regulates the reference voltage to a desired voltage and supplies the regulated reference voltage to the voltage-drop regulator.
FIG. 1 is a schematic block diagram of a conventional internal supply voltage generating circuit 50. The internal supply voltage generating circuit 50 includes a reference voltage generating circuit 51, an internal reference generating circuit 52 and a voltage-drop regulator 53.
The reference voltage generating circuit 51 generates a desired first reference voltage Vflat1 from an external supply voltage Vcc and supplies the first reference voltage Vflat1 to the internal reference generating circuit 52. The internal reference generating circuit 52 generates a second reference voltage Vflat2 using the first reference voltage Vflat1.
As shown in FIG. 2, the internal reference generating circuit 52 includes a differential amplifier 56, a driver 57, a trimming circuit 58 and a phase compensation circuit 59.
The differential amplifier 56 includes a differential amplification section which comprises a first N channel MOS (NMOS) transistor Q1 and a second NMOS transistor Q2, as shown in FIG. 3. The sources of the NMOS transistors Q1 and Q2 are grounded via a current-controlling NMOS transistor Q3. The gate of the NMOS transistor Q3 is connected to the gate of the first NMOS transistor Q1.
The drains of the NMOS transistors Q1 and Q2 are connected to an external supply voltage Vcc via P channel MOS (PMOS) transistors Q4 and Q5 respectively. The gates of the PMOS transistors Q4 and Q5 are connected together to the drain of the second NMOS transistor Q2.
The first reference voltage Vflat1 from the reference voltage generating circuit 51 is supplied to the gate of the first NMOS transistor Q1. A feedback voltage Vf from the trimming circuit 58 is supplied to the gate of the second NMOS transistor Q2. The drain of the first NMOS transistor Q1 also serves as the output terminal of the differential amplifier 56, which is connected to the driver 57.
The driver 57 includes a PMOS transistor Q6 whose gate is supplied with an output voltage Vout of the differential amplifier 56. The source of the PMOS transistor Q6 is connected to the external supply voltage Vcc and the drain of the PMOS transistor Q6 is connected to the voltage-drop regulator 53. The second reference voltage Vflat2 is supplied to the voltage-drop regulator 53 (in FIG. 1) from the drain of the PMOS transistor Q6. The drain of the PMOS transistor Q6 is grounded via the trimming circuit 58.
The trimming circuit 58 includes a voltage dividing circuit, which includes four resistors R1 to R4, and a selection circuit. The selection circuit includes three transfer gates G1 to G3, each connected between the individual nodes between one of the resistors R1-R4 of the voltage dividing circuit and the gate of the second NMOS transistor Q2 of the differential amplifier 56. One of the three transfer gates G1-G3 is turned on by selection signals xcfx861 to xcfx863 and the remaining two transfer gates are turned off.
The divided voltage, which is produced by the voltage dividing circuit, is supplied via the turned-on transfer gate to the non-inverting input terminal (the gate of the second NMOS transistor Q2) of the differential amplifier 56 as the feedback voltage Vf.
The drain of the PMOS transistor Q6 is grounded via the phase compensation circuit 59. The phase compensation circuit 59 includes a resistor R5 and a capacitor Cl.
The differential amplifier 56 regulates the second reference voltage Vflat2 by raising or lowering the output voltage, such that the feedback voltage Vf substantially coincides with the first reference voltage Vflat1. That is, the differential amplifier 56 detects whether the second reference voltage Vflat2 is a predetermined voltage during a test conducted before shipment. When the second reference voltage Vflat2 is not the predetermined voltage, one of the three transfer gates G1-G3 is turned on to regulate the feedback voltage Vf, so that the second reference voltage Vflat2 is adjusted to the predetermined voltage. Therefore, (the voltage-drop regulator 53 produces a highly accurate and stable internal supply voltage Vdd in accordance with the second reference voltage Vflat2 whose productional variation has been compensated.
The phase compensation circuit 59 prevents the internal reference generating circuit 52 from performing an oscillating operation due to the phase shift of the feedback voltage Vf supplied to the differential amplifier 56.
A semiconductor memory device has a plurality of internal supply voltage generating circuits according to the usage of the internal supply voltage Vdd (e.g., the supply voltage for peripheral function circuits, the supply voltage for memory core circuits). Specifically, because of various factors such as the problems related to the withstand voltage and power consumption, which originat from the micro-fabrication process, power supply noise and the set level of the voltage-drop potential, a semiconductor memory device has an internal supply voltage generating circuit for input/output circuits, an internal supply voltage generating circuit for peripheral function circuits and an internal supply voltage generating circuit for a memory array, which are independently provided.
As shown in FIG. 4, a plurality of internal reference generating circuits 64, 65 and 66 are connected to one reference voltage generating circuit 51, and a plurality of voltage-drop regulators 61, 62 and 63 are respectively connected to the internal reference generating circuits 64, 65 and 66. The internal reference generating circuits 64, 65 and 66 respectively generate second reference voltages Vflat2a, Vflat2b and Vflat2c using a first reference voltage Vflat1. The voltage-drop regulators 61, 62 and 63 respectively generate internal supply voltages Vdda, Vddb and Vddc from the second reference voltages Vflat2a, Vflat2b and Vflat2c. 
In this case, however, the provision of the plurality of internal reference generating circuits 64, 65 and 66 increases the circuit area.
As a solution to this shortcoming, as shown in FIG. 5, a single internal reference generating circuit 67, which generates a plurality of second reference voltages Vflat2a, Vflat2b and Vflat2c, has been proposed. Specifically, the second reference voltage Vflat2a is an output from the drain of the PMOS transistor Q6 of the driver 57. The second reference voltages Vflat2b and Vflat2c are outputs from arbitrary nodes between resistors R11 to R15 of the voltage dividing circuit of the trimming circuit 58.
In the trimming circuit 58, one of the three transfer gates G1-G3 is selected based on a variation in the first reference voltage Vflat1. Therefore, the loads of the voltage-drop regulators 62 and 63 are applied to the non-inverting input terminal of the differential amplifier 56 via the selected transfer gate. This significantly changes the load on the non-inverting input terminal of the differential amplifier 56. The phase compensation circuit 59 cannot compensate for a variation in the load, causing the internal reference generating circuit 67 to oscillate.
To make variations in the internal supply voltages Vdd, Vdda, Vddb and Vddc as small as possible, it is desirable to increase the number of resistors in the voltage dividing circuit of the trimming circuit 58. As shown in FIG. 6, a trimming circuit 70 includes a voltage dividing circuit having seventeen resistors Ra1 to Ra17 and a selection circuit having sixteen transfer gates Ga1 to Ga16. By selecting one of the transfer gates Ga1-Ga16, there are sixteen possible ways of selecting the feedback voltage Vf. This allows a variation in the first reference voltage Vflat1 to be adjusted more precisely, thus reducing variations in the internal supply voltages Vdd, Vdda, Vddb and Vddc. However, the overall circuit area is increased by the increases in the number of resistors in the voltage dividing circuit, the number of transfer gates in the selection circuit and the number of signal lines for the sixteen transfer gates Ga1-Ga16.
Accordingly, it is an object of the present invention to provide an internal supply voltage generating circuit that prevents the circuit area from increasing, reduces a variation in a load when regulating a feedback voltage, and generates a plurality of highly accurate internal supply voltages.
In one aspect of the present invention, an embodiment of an internal supply voltage generating circuit is provided. The internal supply voltage generating circuit includes a level trimming circuit for regulating a first reference voltage and generating a predetermined second reference voltage, and an internal reference voltage generating circuit. The latter is connected to the level trimming circuit, for generating one or more internal reference voltages using the predetermined second reference voltage.
In another aspect of the present invention, another embodiment of an internal supply voltage generating circuit is provided. The internal supply voltage generating circuit includes a level trimming circuit for regulating a first reference voltage and generating a predetermined second reference voltage. The level trimming circuit includes a voltage dividing circuit for dividing the second reference voltage and generating a plurality of divided voltages. The level trimming circuit regulates the first reference voltage using at least one divided voltage selected from the plurality of divided voltages as a feedback voltage. An internal reference voltage generating circuit is connected to the level trimming circuit to generate one or more internal supply voltages using the predetermined second reference voltage. A phase compensation circuit is connected between the level trimming circuit and the internal reference voltage generating circuit to compensate for a phase shift of the feedback voltage.
In yet another aspect of the present invention, a method for generating an internal supply voltage is provided. First, a first reference voltage is generated from an external supply voltage, and a predetermined second reference voltage is generated by regulating the first reference voltage. Compensating for a phase shift of the predetermined second reference voltage is performed to generate a compensated predetermined second reference voltage. A plurality of internal reference voltages are generated using the compensated predetermined second reference voltage. Then, a plurality of internal supply voltages are generated using the plurality of internal reference voltages.
Other aspects and advantages of the invention will become apparent from the following description, taken in conjunction with the accompanying drawings, illustrating by way of example the principles of the invention.